From 9605f5ab8c72cbfeab03bed9220849b44d5066b7 Mon Sep 17 00:00:00 2001
From: Myron Stowe <mstowe@redhat.com>
Date: Tue, 25 Mar 2025 08:51:02 -0600
Subject: [PATCH] dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent
JIRA: https://issues.redhat.com/browse/RHEL-83611
Upstream Status: 04aa999eb96fdc8d3cf2b2d98363d6372befaef2
commit 04aa999eb96fdc8d3cf2b2d98363d6372befaef2
Author: Conor Dooley <conor.dooley@microchip.com>
Date: Fri Oct 11 15:00:43 2024 +0100
dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent
PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
Link: https://lore.kernel.org/r/20241011140043.1250030-4-daire.mcnamara@microchip.com
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Myron Stowe <mstowe@redhat.com>
---
Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 2e15475697029..103574d18dbc2 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -50,6 +50,8 @@ properties:
items:
pattern: '^fic[0-3]$'
+ dma-coherent: true
+
ranges:
minItems: 1
maxItems: 3
--
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