openvswitch-2.15.0.patch

+#include <ddk/ndisguid.h>
+#else
+#include <ndisguid.h>
+#endif
+
 #include "private.h"
 #include "pci_netuio.h"
 
diff --git a/dpdk/drivers/bus/pci/windows/pci_netuio.h b/dpdk/drivers/bus/pci/windows/pci_netuio.h
index 9a77806b57..2f6c97ea73 100644
--- a/dpdk/drivers/bus/pci/windows/pci_netuio.h
+++ b/dpdk/drivers/bus/pci/windows/pci_netuio.h
@@ -5,6 +5,7 @@
 #ifndef _PCI_NETUIO_H_
 #define _PCI_NETUIO_H_
 
+#if !defined(NTDDI_WIN10_FE) || NTDDI_VERSION < NTDDI_WIN10_FE
 /* GUID definition for device class netUIO */
 DEFINE_GUID(GUID_DEVCLASS_NETUIO, 0x78912bc1, 0xcb8e, 0x4b28,
 	0xa3, 0x29, 0xf3, 0x22, 0xeb, 0xad, 0xbe, 0x0f);
@@ -12,6 +13,7 @@ DEFINE_GUID(GUID_DEVCLASS_NETUIO, 0x78912bc1, 0xcb8e, 0x4b28,
 /* GUID definition for the netuio device interface */
 DEFINE_GUID(GUID_DEVINTERFACE_NETUIO, 0x08336f60, 0x0679, 0x4c6c,
 	0x85, 0xd2, 0xae, 0x7c, 0xed, 0x65, 0xff, 0xf7);
+#endif
 
 /* IOCTL code definitions */
 #define IOCTL_NETUIO_MAP_HW_INTO_USERSPACE \
diff --git a/dpdk/drivers/common/mlx5/linux/meson.build b/dpdk/drivers/common/mlx5/linux/meson.build
index 63b78e4bce..fa9686fdaf 100644
--- a/dpdk/drivers/common/mlx5/linux/meson.build
+++ b/dpdk/drivers/common/mlx5/linux/meson.build
@@ -19,7 +19,8 @@ endif
 libnames = [ 'mlx5', 'ibverbs' ]
 libs = []
 foreach libname:libnames
-	lib = dependency('lib' + libname, static:static_ibverbs, required:false)
+	lib = dependency('lib' + libname, static:static_ibverbs,
+			required:false, method: 'pkg-config')
 	if not lib.found() and not static_ibverbs
 		lib = cc.find_library(libname, required:false)
 	endif
diff --git a/dpdk/drivers/common/mlx5/linux/mlx5_nl.c b/dpdk/drivers/common/mlx5/linux/mlx5_nl.c
index 40d8620300..ef7a521379 100644
--- a/dpdk/drivers/common/mlx5/linux/mlx5_nl.c
+++ b/dpdk/drivers/common/mlx5/linux/mlx5_nl.c
@@ -758,11 +758,21 @@ mlx5_nl_mac_addr_sync(int nlsk_fd, unsigned int iface_idx,
 				break;
 		if (j != n)
 			continue;
-		/* Find the first entry available. */
-		for (j = 0; j != n; ++j) {
-			if (rte_is_zero_ether_addr(&mac_addrs[j])) {
-				mac_addrs[j] = macs[i];
-				break;
+		if (rte_is_multicast_ether_addr(&macs[i])) {
+			/* Find the first entry available. */
+			for (j = MLX5_MAX_UC_MAC_ADDRESSES; j != n; ++j) {
+				if (rte_is_zero_ether_addr(&mac_addrs[j])) {
+					mac_addrs[j] = macs[i];
+					break;
+				}
+			}
+		} else {
+			/* Find the first entry available. */
+			for (j = 0; j != MLX5_MAX_UC_MAC_ADDRESSES; ++j) {
+				if (rte_is_zero_ether_addr(&mac_addrs[j])) {
+					mac_addrs[j] = macs[i];
+					break;
+				}
 			}
 		}
 	}
diff --git a/dpdk/drivers/common/mlx5/mlx5_devx_cmds.c b/dpdk/drivers/common/mlx5/mlx5_devx_cmds.c
index 9c1d1883ea..eafee65f22 100644
--- a/dpdk/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/dpdk/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -720,6 +720,11 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
 	attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 					   general_obj_types) &
 				MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
+	attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
+	attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
+						mini_cqe_resp_flow_tag);
+	attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
+						 mini_cqe_resp_l3_l4_tag);
 	if (attr->qos.sup) {
 		MLX5_SET(query_hca_cap_in, in, op_mod,
 			 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
@@ -1558,7 +1563,8 @@ mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
 	} else {
 		MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
 	}
-	MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
+	MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
+				     MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
 	MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
 	MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
 	MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
@@ -1571,7 +1577,6 @@ mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
 		 attr->mini_cqe_res_format);
 	MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
 		 attr->mini_cqe_res_format_ext);
-	MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
 	if (attr->q_umem_valid) {
 		MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
 		MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
diff --git a/dpdk/drivers/common/mlx5/mlx5_devx_cmds.h b/dpdk/drivers/common/mlx5/mlx5_devx_cmds.h
index 726e9f5192..78202eba9d 100644
--- a/dpdk/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/dpdk/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -115,6 +115,9 @@ struct mlx5_hca_attr {
 	uint32_t regex:1;
 	uint32_t regexp_num_of_engines;
 	uint32_t log_max_ft_sampler_num:8;
+	uint32_t cqe_compression:1;
+	uint32_t mini_cqe_resp_flow_tag:1;
+	uint32_t mini_cqe_resp_l3_l4_tag:1;
 	struct mlx5_hca_qos_attr qos;
 	struct mlx5_hca_vdpa_attr vdpa;
 };
@@ -267,7 +270,6 @@ struct mlx5_devx_cq_attr {
 	uint32_t cqe_comp_en:1;
 	uint32_t mini_cqe_res_format:2;
 	uint32_t mini_cqe_res_format_ext:2;
-	uint32_t cqe_size:3;
 	uint32_t log_cq_size:5;
 	uint32_t log_page_size:5;
 	uint32_t uar_page_id;
diff --git a/dpdk/drivers/common/mlx5/mlx5_prm.h b/dpdk/drivers/common/mlx5/mlx5_prm.h
index 58d180486e..00b425ac85 100644
--- a/dpdk/drivers/common/mlx5/mlx5_prm.h
+++ b/dpdk/drivers/common/mlx5/mlx5_prm.h
@@ -600,7 +600,7 @@ typedef uint8_t u8;
 
 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
-#define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
+#define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
 				  (&(__mlx5_nullp(typ)->fld)))
 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 				    (__mlx5_bit_off(typ, fld) & 0x1f))
@@ -1364,7 +1364,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
 	u8 num_of_uars_per_page[0x20];
 	u8 flex_parser_protocols[0x20];
 	u8 reserved_at_560[0x20];
-	u8 reserved_at_580[0x3c];
+	u8 reserved_at_580[0x39];
+	u8 mini_cqe_resp_l3_l4_tag[0x1];
+	u8 mini_cqe_resp_flow_tag[0x1];
+	u8 enhanced_cqe_compression[0x1];
 	u8 mini_cqe_resp_stride_index[0x1];
 	u8 cqe_128_always[0x1];
 	u8 cqe_compression_128[0x1];
diff --git a/dpdk/drivers/common/octeontx2/otx2_io_arm64.h b/dpdk/drivers/common/octeontx2/otx2_io_arm64.h
index b5c85d9a6e..34268e3af3 100644
--- a/dpdk/drivers/common/octeontx2/otx2_io_arm64.h
+++ b/dpdk/drivers/common/octeontx2/otx2_io_arm64.h
@@ -21,6 +21,12 @@
 #define otx2_prefetch_store_keep(ptr) ({\
 	asm volatile("prfm pstl1keep, [%x0]\n" : : "r" (ptr)); })
 
+#if defined(__ARM_FEATURE_SVE)
+#define __LSE_PREAMBLE " .cpu  generic+lse+sve\n"
+#else
+#define __LSE_PREAMBLE " .cpu  generic+lse\n"
+#endif
+
 static __rte_always_inline uint64_t
 otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)
 {
@@ -28,7 +34,7 @@ otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr)
 
 	/* Atomic add with no ordering */
 	asm volatile (
-		".cpu  generic+lse\n"
+		__LSE_PREAMBLE
 		"ldadd %x[i], %x[r], [%[b]]"
 		: [r] "=r" (result), "+m" (*ptr)
 		: [i] "r" (incr), [b] "r" (ptr)
@@ -43,7 +49,7 @@ otx2_atomic64_add_sync(int64_t incr, int64_t *ptr)
 
 	/* Atomic add with ordering */
 	asm volatile (
-		".cpu  generic+lse\n"
+		__LSE_PREAMBLE
 		"ldadda %x[i], %x[r], [%[b]]"
 		: [r] "=r" (result), "+m" (*ptr)
 		: [i] "r" (incr), [b] "r" (ptr)
@@ -57,7 +63,7 @@ otx2_lmt_submit(rte_iova_t io_address)
 	uint64_t result;
 
 	asm volatile (
-		".cpu  generic+lse\n"
+		__LSE_PREAMBLE
 		"ldeor xzr,%x[rf],[%[rs]]" :
 		 [rf] "=r"(result): [rs] "r"(io_address));
 	return result;
@@ -69,7 +75,7 @@ otx2_lmt_submit_release(rte_iova_t io_address)
 	uint64_t result;
 
 	asm volatile (
-		".cpu  generic+lse\n"
+		__LSE_PREAMBLE
 		"ldeorl xzr,%x[rf],[%[rs]]" :
 		 [rf] "=r"(result) : [rs] "r"(io_address));
 	return result;
@@ -104,4 +110,5 @@ otx2_lmt_mov_seg(void *out, const void *in, const uint16_t segdw)
 		dst128[i] = src128[i];
 }
 
+#undef __LSE_PREAMBLE
 #endif /* _OTX2_IO_ARM64_H_ */
diff --git a/dpdk/drivers/common/qat/meson.build b/dpdk/drivers/common/qat/meson.build
index 29e1299f20..b2915c91fe 100644
--- a/dpdk/drivers/common/qat/meson.build
+++ b/dpdk/drivers/common/qat/meson.build
@@ -23,7 +23,7 @@ if disabled_drivers.contains(qat_compress_path)
 			'Explicitly disabled via build config')
 endif
 
-libcrypto = dependency('libcrypto', required: false)
+libcrypto = dependency('libcrypto', required: false, method: 'pkg-config')
 if qat_crypto and not libcrypto.found()
 	qat_crypto = false
 	dpdk_drvs_disabled += qat_crypto_path
diff --git a/dpdk/drivers/common/sfc_efx/base/ef10_nic.c b/dpdk/drivers/common/sfc_efx/base/ef10_nic.c
index 68414d9fa9..9dccde9576 100644
--- a/dpdk/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/dpdk/drivers/common/sfc_efx/base/ef10_nic.c
@@ -1423,11 +1423,19 @@ ef10_get_datapath_caps(
 
 #if EFSYS_OPT_MAE
 	/*
-	 * Indicate support for MAE.
-	 * MAE is supported by Riverhead boards starting with R2,
-	 * and it is required that FW is built with MAE support, too.
+	 * Check support for EF100 Match Action Engine (MAE).
+	 * MAE hardware is present on Riverhead boards (from R2),
+	 * and on Keystone, and requires support in firmware.
+	 *
+	 * MAE control operations require MAE control privilege,
+	 * which is not available for VFs.
+	 *
+	 * Privileges can change dynamically at runtime: we assume
+	 * MAE support requires the privilege is granted initially,
+	 * and ignore later dynamic changes.
 	 */
-	if (CAP_FLAGS3(req, MAE_SUPPORTED))
+	if (CAP_FLAGS3(req, MAE_SUPPORTED) &&
+	    EFX_MCDI_HAVE_PRIVILEGE(encp->enc_privilege_mask, MAE))
 		encp->enc_mae_supported = B_TRUE;
 	else
 		encp->enc_mae_supported = B_FALSE;
@@ -1896,6 +1904,18 @@ efx_mcdi_nic_board_cfg(
 
 	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
 
+	/*
+	 * Get the current privilege mask. Note that this may be modified
+	 * dynamically, so for most cases the value is informational only.
+	 * If the privilege being discovered can't be granted dynamically,
+	 * it's fine to rely on the value. In all other cases, DO NOT use
+	 * the privilege mask to check for sufficient privileges, as that
+	 * can result in time-of-check/time-of-use bugs.
+	 */
+	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
+		goto fail6;
+	encp->enc_privilege_mask = mask;
+
 	/* Board configuration (legacy) */
 	rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
 	if (rc != 0) {
@@ -1903,14 +1923,14 @@ efx_mcdi_nic_board_cfg(
 		if (rc == EACCES)
 			board_type = 0;
 		else
-			goto fail6;
+			goto fail7;
 	}
 
 	encp->enc_board_type = board_type;
 
 	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
 	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-		goto fail7;
+		goto fail8;
 
 	/*
 	 * Firmware with support for *_FEC capability bits does not
@@ -1929,18 +1949,18 @@ efx_mcdi_nic_board_cfg(
 
 	/* Obtain the default PHY advertised capabilities */
 	if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-		goto fail8;
+		goto fail9;
 	epp->ep_default_adv_cap_mask = els.epls.epls_adv_cap_mask;
 	epp->ep_adv_cap_mask = els.epls.epls_adv_cap_mask;
 
 	/* Check capabilities of running datapath firmware */
 	if ((rc = ef10_get_datapath_caps(enp)) != 0)
-		goto fail9;
+		goto fail10;
 
 	/* Get interrupt vector limits */
 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
 		if (EFX_PCI_FUNCTION_IS_PF(encp))
-			goto fail10;
+			goto fail11;
 
 		/* Ignore error (cannot query vector limits from a VF). */
 		base = 0;
@@ -1949,16 +1969,6 @@ efx_mcdi_nic_board_cfg(
 	encp->enc_intr_vec_base = base;
 	encp->enc_intr_limit = nvec;
 
-	/*
-	 * Get the current privilege mask. Note that this may be modified
-	 * dynamically, so this value is informational only. DO NOT use
-	 * the privilege mask to check for sufficient privileges, as that
-	 * can result in time-of-check/time-of-use bugs.
-	 */
-	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-		goto fail11;
-	encp->enc_privilege_mask = mask;
-
 	return (0);
 
 fail11:
diff --git a/dpdk/drivers/common/sfc_efx/base/efx.h b/dpdk/drivers/common/sfc_efx/base/efx.h
index 3b40e28b4e..ccf9c7ab8a 100644
--- a/dpdk/drivers/common/sfc_efx/base/efx.h
+++ b/dpdk/drivers/common/sfc_efx/base/efx.h
@@ -4283,6 +4283,11 @@ efx_mae_action_set_specs_equal(
  * Conduct a comparison to check whether two match specifications
  * of equal rule type (action / outer) and priority would map to
  * the very same rule class from the firmware's standpoint.
+ *
+ * For match specification fields that are not supported by firmware,
+ * the rule class only matches if the mask/value pairs for that field
+ * are equal. Clients should use efx_mae_match_spec_is_valid() before
+ * calling this API to detect usage of unsupported fields.
  */
 LIBEFX_API
 extern	__checkReturn			efx_rc_t
diff --git a/dpdk/drivers/common/sfc_efx/base/efx_mae.c b/dpdk/drivers/common/sfc_efx/base/efx_mae.c
index ee0a3d3196..338a0013f9 100644
--- a/dpdk/drivers/common/sfc_efx/base/efx_mae.c
+++ b/dpdk/drivers/common/sfc_efx/base/efx_mae.c
@@ -463,6 +463,10 @@ typedef enum efx_mae_field_endianness_e {
  * The information in it is meant to be used internally by
  * APIs for addressing a given field in a mask-value pairs
  * structure and for validation purposes.
+ *
+ * A field may have an alternative one. This structure
+ * has additional members to reference the alternative
+ * field's mask. See efx_mae_match_spec_is_valid().
  */
 typedef struct efx_mae_mv_desc_s {
 	efx_mae_field_cap_id_t		emmd_field_cap_id;
@@ -472,6 +476,14 @@ typedef struct efx_mae_mv_desc_s {
 	size_t				emmd_mask_size;
 	size_t				emmd_mask_offset;
 
+	/*
+	 * Having the alternative field's mask size set to 0
+	 * means that there's no alternative field specified.
+	 */
+	size_t				emmd_alt_mask_size;
+	size_t				emmd_alt_mask_offset;
+
+	/* Primary field and the alternative one are of the same endianness. */
 	efx_mae_field_endianness_t	emmd_endianness;
 } efx_mae_mv_desc_t;
 
@@ -485,6 +497,7 @@ static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 		MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,		\
 		MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,		\
 		MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,		\
+		0, 0 /* no alternative field */,			\
 		_endianness						\
 	}
 
@@ -522,6 +535,21 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 		MAE_ENC_FIELD_PAIRS_##_name##_OFST,			\
 		MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,			\
 		MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,		\
+		0, 0 /* no alternative field */,			\
+		_endianness						\
+	}
+
+/* Same as EFX_MAE_MV_DESC(), but also indicates an alternative field. */
+#define	EFX_MAE_MV_DESC_ALT(_name, _alt_name, _endianness)		\
+	[EFX_MAE_FIELD_##_name] =					\
+	{								\
+		EFX_MAE_FIELD_ID_##_name,				\
+		MAE_ENC_FIELD_PAIRS_##_name##_LEN,			\
+		MAE_ENC_FIELD_PAIRS_##_name##_OFST,			\
+		MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,			\
+		MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,		\
+		MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_LEN,		\
+		MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_OFST,		\
 		_endianness						\
 	}
 
@@ -533,16 +561,17 @@ static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 	EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 	EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 	EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
-	EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
-	EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
+	EFX_MAE_MV_DESC_ALT(ENC_SRC_IP4_BE, ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
+	EFX_MAE_MV_DESC_ALT(ENC_DST_IP4_BE, ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 	EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 	EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 	EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
-	EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
-	EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
+	EFX_MAE_MV_DESC_ALT(ENC_SRC_IP6_BE, ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
+	EFX_MAE_MV_DESC_ALT(ENC_DST_IP6_BE, ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 	EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 	EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 
+#undef EFX_MAE_MV_DESC_ALT
 #undef EFX_MAE_MV_DESC
 };
 
@@ -564,7 +593,13 @@ efx_mae_mport_by_phy_port(
 	    MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 
 	memset(mportp, 0, sizeof (*mportp));
-	mportp->sel = dword.ed_u32[0];
+	/*
+	 * The constructed DWORD is little-endian,
+	 * but the resulting value is meant to be
+	 * passed to MCDIs, where it will undergo
+	 * host-order to little endian conversion.
+	 */
+	mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 
 	return (0);
 
@@ -601,7 +636,13 @@ efx_mae_mport_by_pcie_function(
 	    MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 
 	memset(mportp, 0, sizeof (*mportp));
-	mportp->sel = dword.ed_u32[0];
+	/*
+	 * The constructed DWORD is little-endian,
+	 * but the resulting value is meant to be
+	 * passed to MCDIs, where it will undergo
+	 * host-order to little endian conversion.
+	 */
+	mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 
 	return (0);
 
@@ -644,28 +685,54 @@ efx_mae_match_spec_field_set(
 		goto fail1;
 	}
 
-	if (field_id >= desc_set_nentries) {
+	if ((unsigned int)field_id >= desc_set_nentries) {
 		rc = EINVAL;
 		goto fail2;
 	}
 
-	if (value_size != descp->emmd_value_size) {
+	if (descp->emmd_mask_size == 0) {
+		/* The ID points to a gap in the array of field descriptors. */
 		rc = EINVAL;
 		goto fail3;
 	}
 
-	if (mask_size != descp->emmd_mask_size) {
+	if (value_size != descp->emmd_value_size) {
 		rc = EINVAL;
 		goto fail4;
 	}
 
+	if (mask_size != descp->emmd_mask_size) {
+		rc = EINVAL;
+		goto fail5;
+	}
+
 	if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
+		unsigned int i;
+
 		/*
 		 * The mask/value are in network (big endian) order.
 		 * The MCDI request field is also big endian.
 		 */
-		memcpy(mvp + descp->emmd_value_offset, value, value_size);
-		memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
+
+		EFSYS_ASSERT3U(value_size, ==, mask_size);
+
+		for (i = 0; i < value_size; ++i) {
+			uint8_t *v_bytep = mvp + descp->emmd_value_offset + i;
+			uint8_t *m_bytep = mvp + descp->emmd_mask_offset + i;
+
+			/*
+			 * Apply the mask (which may be all-zeros) to the value.
+			 *
+			 * If this API is provided with some value to set for a
+			 * given field in one specification and with some other
+			 * value to set for this field in another specification,
+			 * then, if the two masks are all-zeros, the field will
+			 * avoid being counted as a mismatch when comparing the
+			 * specifications using efx_mae_match_specs_equal() API.
+			 */
+			*v_bytep = value[i] & mask[i];
+			*m_bytep = mask[i];
+		}
 	} else {
 		efx_dword_t dword;
 
@@ -700,6 +767,8 @@ efx_mae_match_spec_field_set(
 
 	return (0);
 
+fail5:
+	EFSYS_PROBE(fail5);
 fail4:
 	EFSYS_PROBE(fail4);
 fail3:
@@ -760,7 +829,7 @@ efx_mae_match_specs_equal(
 	    ((_mask)[(_bit) / (_mask_page_nbits)] &			\
 		    (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 
-static inline				boolean_t
+static					boolean_t
 efx_mask_is_prefix(
 	__in				size_t mask_nbytes,
 	__in_bcount(mask_nbytes)	const uint8_t *maskp)
@@ -780,7 +849,7 @@ efx_mask_is_prefix(
 	return B_TRUE;
 }
 
-static inline				boolean_t
+static					boolean_t
 efx_mask_is_all_ones(
 	__in				size_t mask_nbytes,
 	__in_bcount(mask_nbytes)	const uint8_t *maskp)
@@ -794,7 +863,7 @@ efx_mask_is_all_ones(
 	return (t == (uint8_t)(~0));
 }
 
-static inline				boolean_t
+static					boolean_t
 efx_mask_is_all_zeros(
 	__in				size_t mask_nbytes,
 	__in_bcount(mask_nbytes)	const uint8_t *maskp)
@@ -844,17 +913,29 @@ efx_mae_match_spec_is_valid(
 	if (field_caps == NULL)
 		return (B_FALSE);
 
-	for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
+	for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
+	     ++field_id) {
 		const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 		efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
+		const uint8_t *alt_m_buf = mvp + descp->emmd_alt_mask_offset;
 		const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
+		size_t alt_m_size = descp->emmd_alt_mask_size;
 		size_t m_size = descp->emmd_mask_size;
 
 		if (m_size == 0)
 			continue; /* Skip array gap */
 
-		if (field_cap_id >= field_ncaps)
-			break;
+		if ((unsigned int)field_cap_id >= field_ncaps) {
+			/*
+			 * The FW has not reported capability status for
+			 * this field. Make sure that its mask is zeroed.
+			 */
+			is_valid = efx_mask_is_all_zeros(m_size, m_buf);
+			if (is_valid != B_FALSE)
+				continue;
+			else
+				break;
+		}
 
 		switch (field_caps[field_cap_id].emfc_support) {
 		case MAE_FIELD_SUPPORTED_MATCH_MASK:
@@ -869,6 +950,19 @@ efx_mae_match_spec_is_valid(
 			break;
 		case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 			is_valid = efx_mask_is_all_ones(m_size, m_buf);
+
+			if ((is_valid == B_FALSE) && (alt_m_size != 0)) {
+				/*
+				 * This field has an alternative one. The FW
+				 * reports ALWAYS for both implying that one
+				 * of them is required to have all-ones mask.
+				 *
+				 * The primary field's mask is incorrect; go
+				 * on to check that of the alternative field.
+				 */
+				is_valid = efx_mask_is_all_ones(alt_m_size,
+								alt_m_buf);
+			}
 			break;
 		case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 		case MAE_FIELD_UNSUPPORTED:
@@ -1274,7 +1368,13 @@ efx_mae_action_set_populate_drop(
 	EFX_POPULATE_DWORD_1(dword,
 	    MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
 
-	mport.sel = dword.ed_u32[0];
+	/*
+	 * The constructed DWORD is little-endian,
+	 * but the resulting value is meant to be
+	 * passed to MCDIs, where it will undergo
+	 * host-order to little endian conversion.
+	 */
+	mport.sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 
 	arg = (const uint8_t *)&mport.sel;
 
@@ -1350,21 +1450,36 @@ efx_mae_match_specs_class_cmp(
 		return (0);
 	}
 
-	for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
+	for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
+	     ++field_id) {
 		const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 		efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
-
-		if (descp->emmd_mask_size == 0)
+		const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
+		const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
+		size_t mask_size = descp->emmd_mask_size;
+		const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
+		const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
+		size_t value_size = descp->emmd_value_size;
+
+		if (mask_size == 0)
 			continue; /* Skip array gap */
 
-		if (field_cap_id >= field_ncaps)
-			break;
+		if ((unsigned int)field_cap_id >= field_ncaps) {
+			/*
+			 * The FW has not reported capability status for this
+			 * field. It's unknown whether any difference between
+			 * the two masks / values affects the class. The only
+			 * case when the class must be the same is when these
+			 * mask-value pairs match. Otherwise, report mismatch.
+			 */
+			if ((memcmp(lmaskp, rmaskp, mask_size) == 0) &&
+			    (memcmp(lvalp, rvalp, value_size) == 0))
+				continue;
+			else
+				break;
+		}
 
 		if (field_caps[field_cap_id].emfc_mask_affects_class) {
-			const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
-			const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
-			size_t mask_size = descp->emmd_mask_size;
-
 			if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
 				have_same_class = B_FALSE;
 				break;
@@ -1372,10 +1487,6 @@ efx_mae_match_specs_class_cmp(
 		}
 
 		if (field_caps[field_cap_id].emfc_match_affects_class) {
-			const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
-			const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
-			size_t value_size = descp->emmd_value_size;
-
 			if (memcmp(lvalp, rvalp, value_size) != 0) {
 				have_same_class = B_FALSE;
 				break;
diff --git a/dpdk/drivers/common/sfc_efx/base/efx_regs_mcdi.h b/dpdk/drivers/common/sfc_efx/base/efx_regs_mcdi.h
index 0388acf723..689a491d05 100644
--- a/dpdk/drivers/common/sfc_efx/base/efx_regs_mcdi.h
+++ b/dpdk/drivers/common/sfc_efx/base/efx_regs_mcdi.h
@@ -20349,6 +20349,8 @@
  * SF-117064-DG for background).
  */
 #define	MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
+/* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
+#define	MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
 /* enum: Set this bit to indicate that a new privilege mask is to be set,
  * otherwise the command will only read the existing mask.
  */
@@ -26823,7 +26825,7 @@
 #define	MC_CMD_MAE_GET_AR_CAPS 0x141
 #undef	MC_CMD_0x141_PRIVILEGE_CTG
 
-#define	MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x141_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_GET_AR_CAPS_IN msgrequest */
 #define	MC_CMD_MAE_GET_AR_CAPS_IN_LEN 0
@@ -26855,7 +26857,7 @@
 #define	MC_CMD_MAE_GET_OR_CAPS 0x142
 #undef	MC_CMD_0x142_PRIVILEGE_CTG
 
-#define	MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x142_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_GET_OR_CAPS_IN msgrequest */
 #define	MC_CMD_MAE_GET_OR_CAPS_IN_LEN 0
@@ -26885,7 +26887,7 @@
 #define	MC_CMD_MAE_COUNTER_ALLOC 0x143
 #undef	MC_CMD_0x143_PRIVILEGE_CTG
 
-#define	MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x143_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_COUNTER_ALLOC_IN msgrequest */
 #define	MC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4
@@ -26928,7 +26930,7 @@
 #define	MC_CMD_MAE_COUNTER_FREE 0x144
 #undef	MC_CMD_0x144_PRIVILEGE_CTG
 
-#define	MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x144_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_COUNTER_FREE_IN msgrequest */
 #define	MC_CMD_MAE_COUNTER_FREE_IN_LENMIN 8
@@ -26993,6 +26995,9 @@
  * delivering packets to the current queue first.
  */
 #define	MC_CMD_MAE_COUNTERS_STREAM_START 0x151
+#undef	MC_CMD_0x151_PRIVILEGE_CTG
+
+#define	MC_CMD_0x151_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_COUNTERS_STREAM_START_IN msgrequest */
 #define	MC_CMD_MAE_COUNTERS_STREAM_START_IN_LEN 8
@@ -27026,6 +27031,9 @@
  * Stop streaming counter values to the specified RxQ.
  */
 #define	MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
+#undef	MC_CMD_0x152_PRIVILEGE_CTG
+
+#define	MC_CMD_0x152_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_COUNTERS_STREAM_STOP_IN msgrequest */
 #define	MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_LEN 2
@@ -27052,6 +27060,9 @@
  * MAE_COUNTERS_PACKETISER_STREAM_START/PACKET_SIZE and rung the doorbell.
  */
 #define	MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
+#undef	MC_CMD_0x153_PRIVILEGE_CTG
+
+#define	MC_CMD_0x153_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN msgrequest */
 #define	MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4
@@ -27070,7 +27081,7 @@
 #define	MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
 #undef	MC_CMD_0x148_PRIVILEGE_CTG
 
-#define	MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x148_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN msgrequest */
 #define	MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4
@@ -27103,7 +27114,7 @@
 #define	MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
 #undef	MC_CMD_0x149_PRIVILEGE_CTG
 
-#define	MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x149_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN msgrequest */
 #define	MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_LENMIN 8
@@ -27132,7 +27143,7 @@
 #define	MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
 #undef	MC_CMD_0x14a_PRIVILEGE_CTG
 
-#define	MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x14a_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ENCAP_HEADER_FREE_IN msgrequest */
 #define	MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4
@@ -27170,7 +27181,7 @@
 #define	MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
 #undef	MC_CMD_0x15e_PRIVILEGE_CTG
 
-#define	MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x15e_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_MAC_ADDR_ALLOC_IN msgrequest */
 #define	MC_CMD_MAE_MAC_ADDR_ALLOC_IN_LEN 6
@@ -27195,7 +27206,7 @@
 #define	MC_CMD_MAE_MAC_ADDR_FREE 0x15f
 #undef	MC_CMD_0x15f_PRIVILEGE_CTG
 
-#define	MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x15f_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_MAC_ADDR_FREE_IN msgrequest */
 #define	MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4
@@ -27232,7 +27243,7 @@
 #define	MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
 #undef	MC_CMD_0x14d_PRIVILEGE_CTG
 
-#define	MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x14d_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ACTION_SET_ALLOC_IN msgrequest */
 #define	MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN 44
@@ -27317,7 +27328,7 @@
 #define	MC_CMD_MAE_ACTION_SET_FREE 0x14e
 #undef	MC_CMD_0x14e_PRIVILEGE_CTG
 
-#define	MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x14e_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ACTION_SET_FREE_IN msgrequest */
 #define	MC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4
@@ -27355,7 +27366,7 @@
 #define	MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
 #undef	MC_CMD_0x14f_PRIVILEGE_CTG
 
-#define	MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x14f_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN msgrequest */
 #define	MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LENMIN 8
@@ -27398,7 +27409,7 @@
 #define	MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
 #undef	MC_CMD_0x150_PRIVILEGE_CTG
 
-#define	MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x150_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ACTION_SET_LIST_FREE_IN msgrequest */
 #define	MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4
@@ -27435,7 +27446,7 @@
 #define	MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
 #undef	MC_CMD_0x15a_PRIVILEGE_CTG
 
-#define	MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+#define	MC_CMD_0x15a_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_OUTER_RULE_INSERT_IN msgrequest */
 #define	MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMIN 16
@@ -27495,7 +27506,7 @@
 #define	MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
 #undef	MC_CMD_0x15b_PRIVILEGE_CTG
 
-#define	MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_ADMIN
+#define	MC_CMD_0x15b_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_OUTER_RULE_REMOVE_IN msgrequest */
 #define	MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4
@@ -27577,7 +27588,7 @@
 #define	MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
 #undef	MC_CMD_0x15c_PRIVILEGE_CTG
 
-#define	MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x15c_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ACTION_RULE_INSERT_IN msgrequest */
 #define	MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMIN 28
@@ -27618,7 +27629,7 @@
 #define	MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
 #undef	MC_CMD_0x15d_PRIVILEGE_CTG
 
-#define	MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x15d_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ACTION_RULE_UPDATE_IN msgrequest */
 #define	MC_CMD_MAE_ACTION_RULE_UPDATE_IN_LEN 24
@@ -27639,7 +27650,7 @@
 #define	MC_CMD_MAE_ACTION_RULE_DELETE 0x155
 #undef	MC_CMD_0x155_PRIVILEGE_CTG
 
-#define	MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x155_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_ACTION_RULE_DELETE_IN msgrequest */
 #define	MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4
@@ -27696,7 +27707,7 @@
 #define	MC_CMD_MAE_MPORT_ALLOC 0x163
 #undef	MC_CMD_0x163_PRIVILEGE_CTG
 
-#define	MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x163_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_MPORT_ALLOC_IN msgrequest */
 #define	MC_CMD_MAE_MPORT_ALLOC_IN_LEN 20
@@ -27803,7 +27814,7 @@
 #define	MC_CMD_MAE_MPORT_FREE 0x164
 #undef	MC_CMD_0x164_PRIVILEGE_CTG
 
-#define	MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_GENERAL
+#define	MC_CMD_0x164_PRIVILEGE_CTG SRIOV_CTG_MAE
 
 /* MC_CMD_MAE_MPORT_FREE_IN msgrequest */
 #define	MC_CMD_MAE_MPORT_FREE_IN_LEN 4
@@ -27907,6 +27918,9 @@
 /* MC_CMD_MAE_MPORT_ENUMERATE
  */
 #define	MC_CMD_MAE_MPORT_ENUMERATE 0x17c
+#undef	MC_CMD_0x17c_PRIVILEGE_CTG
+
+#define	MC_CMD_0x17c_PRIVILEGE_CTG SRIOV_CTG_GENERAL
 
 /* MC_CMD_MAE_MPORT_ENUMERATE_IN msgrequest */
 #define	MC_CMD_MAE_MPORT_ENUMERATE_IN_LEN 0
diff --git a/dpdk/drivers/compress/isal/meson.build b/dpdk/drivers/compress/isal/meson.build
index 5ee17e28f5..d847c2ea6f 100644
--- a/dpdk/drivers/compress/isal/meson.build
+++ b/dpdk/drivers/compress/isal/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright 2018 Intel Corporation
 
-dep = dependency('libisal', required: false)
+dep = dependency('libisal', required: false, method: 'pkg-config')
 if not dep.found()
 	build = false
 	reason = 'missing dependency, "libisal"'
diff --git a/dpdk/drivers/compress/zlib/meson.build b/dpdk/drivers/compress/zlib/meson.build
index b19a6d2b16..82cf0dddd6 100644
--- a/dpdk/drivers/compress/zlib/meson.build
+++ b/dpdk/drivers/compress/zlib/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2018 Cavium Networks
 
-dep = dependency('zlib', required: false)
+dep = dependency('zlib', required: false, method: 'pkg-config')
 if not dep.found()
 	build = false
 	reason = 'missing dependency, "zlib"'
diff --git a/dpdk/drivers/crypto/armv8/meson.build b/dpdk/drivers/crypto/armv8/meson.build
index 3289a2adca..027173bc1e 100644
--- a/dpdk/drivers/crypto/armv8/meson.build
+++ b/dpdk/drivers/crypto/armv8/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2019 Arm Limited
 
-dep = dependency('libAArch64crypto', required: false)
+dep = dependency('libAArch64crypto', required: false, method: 'pkg-config')
 if not dep.found()
 	build = false
 	reason = 'missing dependency, "libAArch64crypto"'
diff --git a/dpdk/drivers/crypto/ccp/meson.build b/dpdk/drivers/crypto/ccp/meson.build
index a0e0b379eb..ff66427ae8 100644
--- a/dpdk/drivers/crypto/ccp/meson.build
+++ b/dpdk/drivers/crypto/ccp/meson.build
@@ -5,7 +5,7 @@ if not is_linux
 	build = false
 	reason = 'only supported on Linux'
 endif
-dep = dependency('libcrypto', required: false)
+dep = dependency('libcrypto', required: false, method: 'pkg-config')
 if not dep.found()
 	build = false
 	reason = 'missing dependency, "libcrypto"'
diff --git a/dpdk/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/dpdk/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 6ff0d833e9..5d91bf910e 100644
--- a/dpdk/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/dpdk/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -1842,7 +1842,7 @@ dpaa2_sec_cipher_init(struct rte_cryptodev *dev,
 	session->ctxt_type = DPAA2_SEC_CIPHER;
 	session->cipher_key.data = rte_zmalloc(NULL, xform->cipher.key.length,
 			RTE_CACHE_LINE_SIZE);
-	if (session->cipher_key.data == NULL) {
+	if (session->cipher_key.data == NULL && xform->cipher.key.length > 0) {
 		DPAA2_SEC_ERR("No Memory for cipher key");
 		rte_free(priv);
 		return -ENOMEM;
diff --git a/dpdk/drivers/crypto/openssl/meson.build b/dpdk/drivers/crypto/openssl/meson.build
index d9ac698971..47fb2bb751 100644
--- a/dpdk/drivers/crypto/openssl/meson.build
+++ b/dpdk/drivers/crypto/openssl/meson.build
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-dep = dependency('libcrypto', required: false)
+dep = dependency('libcrypto', required: false, method: 'pkg-config')
 if not dep.found()
 	build = false
 	reason = 'missing dependency, "libcrypto"'
diff --git a/dpdk/drivers/crypto/qat/meson.build b/dpdk/drivers/crypto/qat/meson.build
index bc90ec44cc..92e0ed6565 100644
--- a/dpdk/drivers/crypto/qat/meson.build
+++ b/dpdk/drivers/crypto/qat/meson.build
@@ -5,7 +5,7 @@
 # driver which comes later. Here we just add our sources files to the list
 build = false
 reason = '' # sentinal value to suppress printout
-dep = dependency('libcrypto', required: false)
+dep = dependency('libcrypto', required: false, method: 'pkg-config')
 qat_includes += include_directories('.')