PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1

JIRA: https://issues.redhat.com/browse/RHEL-83611
Upstream Status: 4eea7596b8fb5c204f7a454a5166ebdcb6b6c72a

commit 4eea7596b8fb5c204f7a454a5166ebdcb6b6c72a
Author: Thippeswamy Havalige <thippesw@amd.com>
Date:   Sun Sep 22 11:43:18 2024 +0530

    PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1

    Add support for the Xilinx Versal CPM5 Root Port Controller 1. The key
    difference between Controller 0 and Controller 1 lies in the
    platform-specific error interrupt bits, which are located at different
    register offsets.

    To handle these differences, updated variant structure to hold the
    following platform-specific details:

    - Interrupt status register offset (ir_status)
    - Interrupt enable register offset (ir_enable)
    - Miscellaneous interrupt values (ir_misc_value)

    The driver differentiates between Controller 0 and Controller 1 using the
    compatible string in the device tree. This ensures that the appropriate
    register offsets are used for each controller, allowing for correct
    handling of platform-specific interrupts and initialization.

    Link: https://lore.kernel.org/r/20240922061318.2653503-3-thippesw@amd.com


Signed-off-by: Thippeswamy Havalige <thippesw@amd.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Signed-off-by: Myron Stowe <mstowe@redhat.com>