PCI: Honor Max Link Speed when determining supported speeds

JIRA: https://issues.redhat.com/browse/RHEL-81906
Upstream Status: 3202ca221578850f34e0fea39dc6cfa745ed7aac

commit 3202ca221578850f34e0fea39dc6cfa745ed7aac
Author: Lukas Wunner <lukas@wunner.de>
Date:   Tue Dec 17 10:51:01 2024 +0100

    PCI: Honor Max Link Speed when determining supported speeds

    The Supported Link Speeds Vector in the Link Capabilities 2 Register
    indicates the *supported* link speeds.  The Max Link Speed field in the
    Link Capabilities Register indicates the *maximum* of those speeds.

    pcie_get_supported_speeds() neglects to honor the Max Link Speed field and
    will thus incorrectly deem higher speeds as supported.  Fix it.

    One user-visible issue addressed here is an incorrect value in the sysfs
    attribute "max_link_speed".

    But the main motivation is a boot hang reported by Niklas:  Intel JHL7540
    "Titan Ridge 2018" Thunderbolt controllers supports 2.5-8 GT/s speeds,
    but indicate 2.5 GT/s as maximum.  Ilpo recalls seeing this on more
    devices.  It can be explained by the controller's Downstream Ports
    supporting 8 GT/s if an Endpoint is attached, but limiting to 2.5 GT/s
    if the port interfaces to a PCIe Adapter, in accordance with USB4 v2
    sec 11.2.1:

       "This section defines the functionality of an Internal PCIe Port that
        interfaces to a PCIe Adapter. [...]
        The Logical sub-block shall update the PCIe configuration registers
        with the following characteristics: [...]
        Max Link Speed field in the Link Capabilities Register set to 0001b
        (data rate of 2.5 GT/s only).
        Note: These settings do not represent actual throughput. Throughput
        is implementation specific and based on the USB4 Fabric performance."

    The present commit is not sufficient on its own to fix Niklas' boot hang,
    but it is a prerequisite:  A subsequent commit will fix the boot hang by
    enabling bandwidth control only if more than one speed is supported.

    The GENMASK() macro used herein specifies 0 as lowest bit, even though
    the Supported Link Speeds Vector ends at bit 1.  This is done on purpose
    to avoid a GENMASK(0, 1) macro if Max Link Speed is zero.  That macro
    would be invalid as the lowest bit is greater than the highest bit.
    Ilpo has witnessed a zero Max Link Speed on Root Complex Integrated
    Endpoints in particular, so it does occur in practice.  (The Link
    Capabilities Register is optional on RCiEPs per PCIe r6.2 sec 7.5.3.)

    Fixes: d2bd39c0456b ("PCI: Store all PCIe Supported Link Speeds")
    Closes: https://lore.kernel.org/r/70829798889c6d779ca0f6cd3260a765780d1369.camel@kernel.org
    Link: https://lore.kernel.org/r/fe03941e3e1cc42fb9bf4395e302bff53ee2198b.1734428762.git.lukas@wunner.de


Reported-by: Niklas Schnelle <niks@kernel.org>
Tested-by: Niklas Schnelle <niks@kernel.org>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>

Signed-off-by: Myron Stowe <mstowe@redhat.com>