This project is mirrored from https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-10.git.
Pull mirroring updated .
- Mar 29, 2025
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 2a93192d2058507b2e39b590fc1efa0e03344136 commit 2a93192d2058507b2e39b590fc1efa0e03344136 Author: Niklas Cassel <cassel@kernel.org> Date: Tue Feb 4 12:06:41 2025 +0100 misc: pci_endpoint_test: Fix pci_endpoint_test_bars_read_bar() error handling Commit f26d37ee9bda ("misc: pci_endpoint_test: Fix IOCTL return value") changed the return value of pci_endpoint_test_bars_read_bar() from false to -EINVAL on error, however, it failed to update the error handling. Fixes: f26d37ee9bda ("misc: pci_endpoint_test: Fix IOCTL return value") Signed-off-by:
Niklas Cassel <cassel@kernel.org> Reviewed-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20250204110640.570823-2-cassel@kernel.org Signed-off-by:
Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by:
Myron Stowe <mstowe@redhat.com>
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 86c2345aff3f5b48b53a73a15ffe6e0930e4170f commit 86c2345aff3f5b48b53a73a15ffe6e0930e4170f Author: Jianfeng Liu <liujianfeng1994@gmail.com> Date: Mon Feb 17 19:51:52 2025 +0800 tools/Makefile: Remove pci target e19bde2269ca ("selftests: Move PCI Endpoint tests from tools/pci to Kselftests") moves tools/pci/ to tools/testing/selftests/pci_endpoint, which causes build failure when running "make pci" under tools: linux/tools$ make pci DESCEND pci make[1]: *** No targets specified and no makefile found. Stop. make: *** [Makefile:73: pci] Error 2 Update the top level tools/Makefile to remove reference to building, installing and cleaning pci components. Link: https://lore.kernel.org/r/20250217115159.537920-1-liujianfeng1994@gmail.com Fixes: e19bde2269ca ("selftests: Move PCI Endpoint tests from tools/pci to Kselftests") Signed-off-by:
Jianfeng Liu <liujianfeng1994@gmail.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Reviewed-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 81f64e925c29fe6e99f04b131fac1935ac931e81 commit 81f64e925c29fe6e99f04b131fac1935ac931e81 Author: Bjorn Helgaas <bhelgaas@google.com> Date: Wed Feb 12 13:35:16 2025 -0600 PCI: Avoid FLR for Mediatek MT7922 WiFi The Mediatek MT7922 WiFi device advertises FLR support, but it apparently does not work, and all subsequent config reads return ~0: pci 0000:01:00.0: [14c3:0616] type 00 class 0x028000 PCIe Endpoint pciback 0000:01:00.0: not ready 65535ms after FLR; giving up After an FLR, pci_dev_wait() waits for the device to become ready. Prior to d591f680 ("PCI: Wait for device readiness with Configuration RRS"), it polls PCI_COMMAND until it is something other that PCI_POSSIBLE_ERROR (~0). If it times out, pci_dev_wait() returns -ENOTTY and __pci_reset_function_locked() tries the next available reset method. Typically this is Secondary Bus Reset, which does work, so the MT7922 is eventually usable. After d591f680, if Configuration Request Retry Status Software Visibility (RRS SV) is enabled, pci_dev_wait() polls PCI_VENDOR_ID until it is something other than the special 0x0001 Vendor ID that indicates a completion with RRS status. When RRS SV is enabled, reads of PCI_VENDOR_ID should return either 0x0001, i.e., the config read was completed with RRS, or a valid Vendor ID. On the MT7922, it seems that all config reads after FLR return ~0 indefinitely. When pci_dev_wait() reads PCI_VENDOR_ID and gets 0xffff, it assumes that's a valid Vendor ID and the device is now ready, so it returns with success. After pci_dev_wait() returns success, we restore config space and continue. Since the MT7922 is not actually ready after the FLR, the restore fails and the device is unusable. We considered changing pci_dev_wait() to continue polling if a PCI_VENDOR_ID read returns either 0x0001 or 0xffff. This "works" as it did before d591f680, although we have to wait for the timeout and then fall back to SBR. But it doesn't work for SR-IOV VFs, which *always* return 0xffff as the Vendor ID. Mark Mediatek MT7922 WiFi devices to avoid the use of FLR completely. This will cause fallback to another reset method, such as SBR. Link: https://lore.kernel.org/r/20250212193516.88741-1-helgaas@kernel.org Fixes: d591f680 ("PCI: Wait for device readiness with Configuration RRS") Link: https://github.com/QubesOS/qubes-issues/issues/9689#issuecomment-2582927149 Link: https://lore.kernel.org/r/Z4pHll_6GX7OUBzQ@mail-itl Signed-off-by:
Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> Cc: stable@vger.kernel.org Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 472ff48e2c09e49f2f90eeb6922f747306559506 commit 472ff48e2c09e49f2f90eeb6922f747306559506 Author: Alex Williamson <alex.williamson@redhat.com> Date: Wed Feb 12 11:53:32 2025 -0700 PCI: Fix BUILD_BUG_ON usage for old gcc As reported in the below link, it seems older versions of gcc cannot determine that the howmany variable is known for all callers. Include a test so that newer compilers can enforce this sanity check and older compilers can still work. Add __always_inline attribute to give the compiler an even better chance to know the inputs. Link: https://lore.kernel.org/r/20250212185337.293023-1-alex.williamson@redhat.com Fixes: 4453f360862e ("PCI: Batch BAR sizing operations") Reported-by:
Oleg Nesterov <oleg@redhat.com> Link: https://lore.kernel.org/all/20250209154512.GA18688@redhat.com Signed-off-by:
Alex Williamson <alex.williamson@redhat.com> Signed-off-by:
Mitchell Augustin <mitchell.augustin@canonical.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 7507eb3e7bfac7c3baef8dd377fdf5871eefd42b commit 7507eb3e7bfac7c3baef8dd377fdf5871eefd42b Author: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Date: Fri Jan 31 17:29:13 2025 +0200 PCI/ASPM: Fix L1SS saving Commit 1db806ec06b7 ("PCI/ASPM: Save parent L1SS config in pci_save_aspm_l1ss_state()") aimed to perform L1SS config save for both the Upstream Port and its upstream bridge when handling an Upstream Port, which matches what the L1SS restore side does. However, parent->state_saved can be set true at an earlier time when the upstream bridge saved other parts of its state. Then later when attempting to save the L1SS config while handling the Upstream Port, parent->state_saved is true in pci_save_aspm_l1ss_state() resulting in early return and skipping saving bridge's L1SS config because it is assumed to be already saved. Later on restore, junk is written into L1SS config which causes issues with some devices. Remove parent->state_saved check and unconditionally save L1SS config also for the upstream bridge from an Upstream Port which ought to be harmless from correctness point of view. With the Upstream Port check now present, saving the L1SS config more than once for the bridge is no longer a problem (unlike when the parent->state_saved check got introduced into the fix during its development). Link: https://lore.kernel.org/r/20250131152913.2507-1-ilpo.jarvinen@linux.intel.com Fixes: 1db806ec06b7 ("PCI/ASPM: Save parent L1SS config in pci_save_aspm_l1ss_state()") Closes: https://bugzilla.kernel.org/show_bug.cgi?id=219731 Reported-by:
Niklāvs Koļesņikovs <pinkflames.linux@gmail.com> Reported by: Rafael J. Wysocki <rafael@kernel.org> Closes: https://lore.kernel.org/r/CAJZ5v0iKmynOQ5vKSQbg1J_FmavwZE-nRONovOZ0mpMVauheWg@mail.gmail.com Reported-by:
Paul Menzel <pmenzel@molgen.mpg.de> Closes: https://lore.kernel.org/r/d7246feb-4f3f-4d0c-bb64-89566b170671@molgen.mpg.de Signed-off-by:
Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: d555ed45a5a10a813528c7685f432369d536ae3d commit d555ed45a5a10a813528c7685f432369d536ae3d Author: Takashi Iwai <tiwai@suse.de> Date: Thu Oct 31 14:42:56 2024 +0100 PCI: Restore original INTX_DISABLE bit by pcim_intx() pcim_intx() tries to restore the INTx bit at removal via devres, but there is a chance that it restores a wrong value. Because the value to be restored is blindly assumed to be the negative of the enable argument, when a driver calls pcim_intx() unnecessarily for the already enabled state, it'll restore to the disabled state in turn. That is, the function assumes the case like: // INTx == 1 pcim_intx(pdev, 0); // old INTx value assumed to be 1 -> correct but it might be like the following, too: // INTx == 0 pcim_intx(pdev, 0); // old INTx value assumed to be 1 -> wrong Also, when a driver calls pcim_intx() multiple times with different enable argument values, the last one will win no matter what value it is. This can lead to inconsistency, e.g. // INTx == 1 pcim_intx(pdev, 0); // OK ... pcim_intx(pdev, 1); // now old INTx wrongly assumed to be 0 This patch addresses those inconsistencies by saving the original INTx state at the first pcim_intx() call. For that, get_or_create_intx_devres() is folded into pcim_intx() caller side; it allows us to simply check the already allocated devres and record the original INTx along with the devres_alloc() call. Link: https://lore.kernel.org/r/20241031134300.10296-1-tiwai@suse.de Fixes: 25216afc ("PCI: Add managed pcim_intx()") Link: https://lore.kernel.org/87v7xk2ps5.wl-tiwai@suse.de Signed-off-by:
Takashi Iwai <tiwai@suse.de> Signed-off-by:
Philipp Stanner <pstanner@redhat.com> Cc: stable@vger.kernel.org # v6.11+ Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: b388face5f169e7a41c1b5e1cdd20515160a83b3 commit b388face5f169e7a41c1b5e1cdd20515160a83b3 Author: Akihiko Odaki <akihiko.odaki@daynix.com> Date: Sun Sep 15 10:36:58 2024 +0900 Documentation: Fix pci=config_acs= example The documentation currently says: config_acs= Format: <ACS flags>@<pci_dev>[; ...] Specify one or more PCI devices (in the format specified above) optionally prepended with flags and separated by semicolons. The respective capabilities will be enabled, disabled or unchanged based on what is specified in flags. (...) For example, pci=config_acs=10x would configure all devices that support ACS to enable P2P Request Redirect, disable Translation Blocking, and leave Source Validation unchanged from whatever power-up or firmware set it to. See the complete documentation at: https://www.kernel.org/doc/html/latest/admin-guide/kernel-parameters.html However, a flag specification always needs to be suffixed with "@" and a PCI valid device address, which is missing in this example. Also, to configure all devices that support ACS, the flag needs to be suffixed with "@pci:0:0", for the ACS support to be enabled. Fix the documentation so the example is correct. Link: https://lore.kernel.org/r/20240915-acs-v1-1-b9ee536ee9bd@daynix.com Signed-off-by:
Akihiko Odaki <akihiko.odaki@daynix.com> [kwilczynski: commit log] Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 188973e3536a18aebee3af486cd3d2ef82b09f88 commit 188973e3536a18aebee3af486cd3d2ef82b09f88 Author: Dongdong Zhang <zhangdongdong@eswincomputing.com> Date: Mon Dec 16 09:35:36 2024 +0800 PCI: Remove redundant PCI_VSEC_HDR and PCI_VSEC_HDR_LEN_SHIFT Remove duplicate macro PCI_VSEC_HDR and its related macro PCI_VSEC_HDR_LEN_SHIFT from pci_regs.h to avoid redundancy and inconsistencies. Update VFIO PCI code to use PCI_VNDR_HEADER and PCI_VNDR_HEADER_LEN() for consistent naming and functionality. These changes aim to streamline header handling while minimizing impact, given the niche usage of these macros in userspace. Link: https://lore.kernel.org/r/20241216013536.4487-1-zhangdongdong@eswincomputing.com Signed-off-by:
Dongdong Zhang <zhangdongdong@eswincomputing.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 816875a468f40a601da001d7518ddbf363381a18 commit 816875a468f40a601da001d7518ddbf363381a18 Author: Wolfram Sang <wsa+renesas@sang-engineering.com> Date: Mon Nov 18 08:29:10 2024 +0100 PCI: Don't include 'pm_wakeup.h' directly The header clearly states that it does not want to be included directly, only via 'device.h'. The 'platform_device.h' works equally well. Thus, remove the direct inclusion. Link: https://lore.kernel.org/r/20241118072917.3853-12-wsa+renesas@sang-engineering.com Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: e10c5cbd1c912c06d887c8a1980ac57e21d87b6f commit e10c5cbd1c912c06d887c8a1980ac57e21d87b6f Author: Lukas Wunner <lukas@wunner.de> Date: Mon Dec 16 20:18:41 2024 +0100 PCI: Update code comment on PCI_EXP_LNKCAP_SLS for PCIe r3.0 Niklas notes that the code comment on the PCI_EXP_LNKCAP_SLS macro is outdated as it reflects the meaning of the field prior to PCIe r3.0. Update it to avoid confusion. Closes: https://lore.kernel.org/r/70829798889c6d779ca0f6cd3260a765780d1369.camel@kernel.org Link: https://lore.kernel.org/r/6152bd17cbe0876365d5f4624fc317529f4bbc85.1734376438.git.lukas@wunner.de Reported-by:
Niklas Schnelle <niks@kernel.org> Signed-off-by:
Lukas Wunner <lukas@wunner.de> Signed-off-by:
Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 4eea7596b8fb5c204f7a454a5166ebdcb6b6c72a commit 4eea7596b8fb5c204f7a454a5166ebdcb6b6c72a Author: Thippeswamy Havalige <thippesw@amd.com> Date: Sun Sep 22 11:43:18 2024 +0530 PCI: xilinx-cpm: Add support for Versal CPM5 Root Port Controller 1 Add support for the Xilinx Versal CPM5 Root Port Controller 1. The key difference between Controller 0 and Controller 1 lies in the platform-specific error interrupt bits, which are located at different register offsets. To handle these differences, updated variant structure to hold the following platform-specific details: - Interrupt status register offset (ir_status) - Interrupt enable register offset (ir_enable) - Miscellaneous interrupt values (ir_misc_value) The driver differentiates between Controller 0 and Controller 1 using the compatible string in the device tree. This ensures that the appropriate register offsets are used for each controller, allowing for correct handling of platform-specific interrupts and initialization. Link: https://lore.kernel.org/r/20240922061318.2653503-3-thippesw@amd.com Signed-off-by:
Thippeswamy Havalige <thippesw@amd.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 5c911b4659d55580a15150b7845f13d04c070112 commit 5c911b4659d55580a15150b7845f13d04c070112 Author: Thippeswamy Havalige <thippesw@amd.com> Date: Sun Sep 22 11:43:17 2024 +0530 dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5 host1 The Xilinx Versal premium series has CPM5 block which supports two typeA Root Port controller functionality at Gen5 speed. Add compatible string to distinguish between two CPM5 rootport controller1. since Legacy and error interrupt register and bits for both the controllers are at different offsets. Link: https://lore.kernel.org/r/20240922061318.2653503-2-thippesw@amd.com Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 500969661b0294e0442bc516a9e272e7e8561d95 commit 500969661b0294e0442bc516a9e272e7e8561d95 Author: Anand Moon <linux.amoon@gmail.com> Date: Mon Dec 2 20:41:44 2024 +0530 PCI: rockchip: Refactor rockchip_pcie_disable_clocks() signature Refactor rockchip_pcie_disable_clocks() to accept a struct rockchip_pcie pointer instead of a void pointer thus improving type safety and code readability by explicitly specifying the expected data type. Link: https://lore.kernel.org/r/20241202151150.7393-4-linux.amoon@gmail.com Signed-off-by:
Anand Moon <linux.amoon@gmail.com> Signed-off-by:
Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 18715931a5c08d199d14df116832d88dc4df48c5 commit 18715931a5c08d199d14df116832d88dc4df48c5 Author: Anand Moon <linux.amoon@gmail.com> Date: Mon Dec 2 20:41:43 2024 +0530 PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function Currently, the driver acquires and asserts/deasserts the resets individually thereby making the driver complex to read. This can be simplified by using the reset_control_bulk() APIs. Use devm_reset_control_bulk_get_exclusive() API to acquire all the resets and use reset_control_bulk_{assert/deassert}() APIs to assert/deassert them in bulk. Following the recommendations in 'Rockchip RK3399 TRM v1.3 Part2': 1. Split the reset controls into two groups as per section '17.5.8.1.1 PCIe as Root Complex'. 2. Deassert the 'Pipe, MGMT Sticky, MGMT, Core' resets in groups as per section '17.5.8.1.1 PCIe as Root Complex'. This is accomplished using the reset_control_bulk APIs. Link: https://lore.kernel.org/r/20241202151150.7393-3-linux.amoon@gmail.com Co-developed-by:
Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: abdd4c8ea7d75308315a15cfb97d2eabfb4d052b commit abdd4c8ea7d75308315a15cfb97d2eabfb4d052b Author: Anand Moon <linux.amoon@gmail.com> Date: Mon Dec 2 20:41:42 2024 +0530 PCI: rockchip: Simplify clock handling by using clk_bulk*() functions Currently, the driver acquires clocks and prepare/enable/disable/unprepare the clocks individually thereby making the driver complex to read. The driver can be simplified by using the clk_bulk*() APIs. Use: - devm_clk_bulk_get_all() API to acquire all the clocks - clk_bulk_prepare_enable() to prepare/enable clocks - clk_bulk_disable_unprepare() APIs to disable/unprepare them in bulk Link: https://lore.kernel.org/r/20241202151150.7393-2-linux.amoon@gmail.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 2d2da5a4c1b4509f6f7e5a8db015cd420144beb4 commit 2d2da5a4c1b4509f6f7e5a8db015cd420144beb4 Author: King Dix <kingdix10@qq.com> Date: Thu Jan 9 08:50:18 2025 +0800 PCI: rcar-ep: Fix incorrect variable used when calling devm_request_mem_region() The rcar_pcie_parse_outbound_ranges() uses the devm_request_mem_region() macro to request a needed resource. A string variable that lives on the stack is then used to store a dynamically computed resource name, which is then passed on as one of the macro arguments. This can lead to undefined behavior. Depending on the current contents of the memory, the manifestations of errors may vary. One possible output may be as follows: $ cat /proc/iomem 30000000-37ffffff : 38000000-3fffffff : Sometimes, garbage may appear after the colon. In very rare cases, if no NULL-terminator is found in memory, the system might crash because the string iterator will overrun which can lead to access of unmapped memory above the stack. Thus, fix this by replacing outbound_name with the name of the previously requested resource. With the changes applied, the output will be as follows: $ cat /proc/iomem 30000000-37ffffff : memory2 38000000-3fffffff : memory3 Fixes: 2a6d0d63 ("PCI: rcar: Add endpoint mode support") Link: https://lore.kernel.org/r/tencent_DBDCC19D60F361119E76919ADAB25EC13C06@qq.com Tested-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by:
King Dix <kingdix10@qq.com> [kwilczynski: commit log] Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 26cdda544479341d73512f5cf9cf4bab080c11c9 commit 26cdda544479341d73512f5cf9cf4bab080c11c9 Author: Liao Chen <liaochen4@huawei.com> Date: Tue Sep 3 13:23:11 2024 +0000 PCI: mvebu: Enable module autoloading Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded based on the alias from of_device_id table. Link: https://lore.kernel.org/r/20240903132311.961646-1-liaochen4@huawei.com Signed-off-by:
Liao Chen <liaochen4@huawei.com> Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 04aa999eb96fdc8d3cf2b2d98363d6372befaef2 commit 04aa999eb96fdc8d3cf2b2d98363d6372befaef2 Author: Conor Dooley <conor.dooley@microchip.com> Date: Fri Oct 11 15:00:43 2024 +0100 dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent PolarFire SoC may be configured in a way that requires non-coherent DMA handling. On RISC-V, buses are coherent by default & the dma-noncoherent property is required to denote buses or devices that are non-coherent. Link: https://lore.kernel.org/r/20241011140043.1250030-4-daire.mcnamara@microchip.com Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 1390a33b3d04fdf6ba4e3e7082107a12027fc188 commit 1390a33b3d04fdf6ba4e3e7082107a12027fc188 Author: Daire McNamara <daire.mcnamara@microchip.com> Date: Fri Oct 11 15:00:42 2024 +0100 PCI: microchip: Set inbound address translation for coherent or non-coherent mode On Microchip PolarFire SoC the PCIe Root Port can be behind one of three general purpose Fabric Interface Controller (FIC) buses that encapsulates an AXI-S bus. Depending on which FIC(s) the Root Port is connected through to CPU space, and what address translation is done by that FIC, the Root Port driver's inbound address translation may vary. For all current supported designs and all future expected designs, inbound address translation done by a FIC on PolarFire SoC varies depending on whether PolarFire SoC is operating in coherent DMA mode or noncoherent DMA mode. The setup of the outbound address translation tables in the Root Port driver only needs to handle these two cases. Setup the inbound address translation tables to one of two address translations, depending on whether the Root Port is being used with coherent DMA or noncoherent DMA. Link: https://lore.kernel.org/r/20241011140043.1250030-3-daire.mcnamara@microchip.com Fixes: 6f15a9c9 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver") Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 17bd5e4dc96c953257eadce111d7b6ef458c6187 commit 17bd5e4dc96c953257eadce111d7b6ef458c6187 Author: Douglas Anderson <dianders@chromium.org> Date: Fri Dec 20 14:52:05 2024 -0800 PCI: mediatek-gen3: Enable async probe by default The mediatek-gen3 driver can run its probe routine fairly slow on some hardware, which adds to the total time it takes for the system start up. Thus, turn on async mode for the probe to avoid blocking the rest of the system. Link: https://lore.kernel.org/r/20241220145205.1.Ibf2563896c3b1fc133bb46d3fc96ad0041763922@changeid Signed-off-by:
Douglas Anderson <dianders@chromium.org> [kwilczynski: commit log] Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 491cb9c5084790aafa02e843349492c284373231 commit 491cb9c5084790aafa02e843349492c284373231 Author: Lorenzo Bianconi <lorenzo@kernel.org> Date: Thu Jan 9 00:30:45 2025 +0100 PCI: mediatek-gen3: Avoid PCIe resetting via PERST# for Airoha EN7581 SoC Airoha EN7581 has a hw bug asserting/releasing PERST# signal causing occasional PCIe link down issues. In order to overcome the problem, PERST# signal is not asserted/released during device probe or suspend/resume phase and the PCIe block is reset using en7523_reset_assert() and en7581_pci_enable(). Introduce flags field in the mtk_gen3_pcie_pdata struct in order to specify per-SoC capabilities. Link: https://lore.kernel.org/r/20250109-pcie-en7581-rst-fix-v4-1-4a45c89fb143@kernel.org Tested-by:
Hui Ma <hui.ma@airoha.com> Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: c98bee18d0a094e37100c85effe5e161418f8644 commit c98bee18d0a094e37100c85effe5e161418f8644 Author: Lorenzo Bianconi <lorenzo@kernel.org> Date: Wed Jan 8 10:50:44 2025 +0100 PCI: mediatek-gen3: Rely on msleep() in mtk_pcie_en7581_power_up() Since mtk_pcie_en7581_power_up() runs in non-atomic context, rely on msleep() routine instead of mdelay(). Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-5-21ac939a3b9b@kernel.org Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 90d4e466c9ea2010f33880a36317a8486ccbe082 commit 90d4e466c9ea2010f33880a36317a8486ccbe082 Author: Lorenzo Bianconi <lorenzo@kernel.org> Date: Wed Jan 8 10:50:43 2025 +0100 PCI: mediatek-gen3: Move reset delay in mtk_pcie_en7581_power_up() Airoha EN7581 has a hw bug asserting/releasing PCIE_PE_RSTB signal causing occasional PCIe link down issues. In order to overcome the problem, PCIe block is reset using REG_PCI_CONTROL (0x88) and REG_RESET_CONTROL (0x834) registers available in the clock module running clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up(). In order to make the code more readable, move the wait for the time needed to complete the PCIe reset from en7581_pci_enable() to mtk_pcie_en7581_power_up(). Reduce reset timeout from 250ms to the standard PCIE_T_PVPERL_MS value (100ms) since it has no impact on the driver behavior. Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-4-21ac939a3b9b@kernel.org Signed-off-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 0c9d2d2ef0d916b490a9222ed20ff4616fca876d commit 0c9d2d2ef0d916b490a9222ed20ff4616fca876d Author: Lorenzo Bianconi <lorenzo@kernel.org> Date: Wed Jan 8 10:50:42 2025 +0100 PCI: mediatek-gen3: Add comment about initialization order in mtk_pcie_en7581_power_up() Add a comment in mtk_pcie_en7581_power_up() to clarify, unlike the other MediaTek Gen3 controllers, the Airoha EN7581 requires PHY initialization and power-on before PHY reset deassert. Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-3-21ac939a3b9b@kernel.org Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: e4c7dfd953f7618f0ccb70d87c1629634f306fab commit e4c7dfd953f7618f0ccb70d87c1629634f306fab Author: Lorenzo Bianconi <lorenzo@kernel.org> Date: Wed Jan 8 10:50:41 2025 +0100 PCI: mediatek-gen3: Move reset/assert callbacks in .power_up() In order to make the code more readable, the reset_control_bulk_assert() function for PHY reset lines is moved to make it pair with reset_control_bulk_deassert() in mtk_pcie_power_up() and mtk_pcie_en7581_power_up(). The same change is done for reset_control_assert() used to assert MAC reset line. Introduce PCIE_MTK_RESET_TIME_US macro for the time needed to complete PCIe reset on MediaTek controller. Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-2-21ac939a3b9b@kernel.org Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 0e7a622da17da0042294860cdb7a2fac091d25b1 commit 0e7a622da17da0042294860cdb7a2fac091d25b1 Author: Lorenzo Bianconi <lorenzo@kernel.org> Date: Wed Jan 8 10:50:40 2025 +0100 PCI: mediatek-gen3: Rely on clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() Replace clk_bulk_prepare() and clk_bulk_enable() with clk_bulk_prepare_enable() in mtk_pcie_en7581_power_up() routine. Link: https://lore.kernel.org/r/20250108-pcie-en7581-fixes-v6-1-21ac939a3b9b@kernel.org Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 149fc35734e50fc3200cf84c8efd711205961636 commit 149fc35734e50fc3200cf84c8efd711205961636 Author: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Date: Sun Jan 12 14:39:03 2025 +0100 PCI: layerscape: Use syscon_regmap_lookup_by_phandle_args Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over syscon_regmap_lookup_by_phandle() combined with getting the syscon argument. Except simpler code this annotates within one line that given phandle has arguments, so grepping for code would be easier. Link: https://lore.kernel.org/r/20250112-syscon-phandle-args-pci-v1-2-fcb6ebcc0afc@linaro.org Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Frank Li <Frank.Li@nxp.com> Acked-by:
Roy Zang <Roy.Zang@nxp.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: b881532991f81f5e3a069fe6d1a3e091400042b5 commit b881532991f81f5e3a069fe6d1a3e091400042b5 Author: Bjorn Helgaas <bhelgaas@google.com> Date: Sat Jan 18 13:55:58 2025 -0600 PCI: imx6: Clean up comments and whitespace For readability, fix typos and comments that needlessly exceed 80 columns. Link: https://lore.kernel.org/r/20250118210727.795559-1-helgaas@kernel.org Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 6dd24b0a858e64f9df596bf7cad2ddb436506f46 commit 6dd24b0a858e64f9df596bf7cad2ddb436506f46 Author: Richard Zhu <hongxing.zhu@nxp.com> Date: Tue Nov 26 15:56:59 2024 +0800 PCI: imx6: Remove surplus imx7d_pcie_init_phy() function This function essentially duplicates imx7d_pcie_enable_ref_clk(). So remove it. Link: https://lore.kernel.org/r/20241126075702.4099164-8-hongxing.zhu@nxp.com Signed-off-by:
Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 93d883f89063744a92006fc356b1c767eb62d950 commit 93d883f89063744a92006fc356b1c767eb62d950 Author: Richard Zhu <hongxing.zhu@nxp.com> Date: Tue Nov 26 15:56:58 2024 +0800 PCI: imx6: Add missing reference clock disable logic Ensure the *_enable_ref_clk() function is symmetric by addressing missing disable parts on some platforms. Fixes: d0a75c79 ("PCI: imx6: Factor out ref clock disable to match enable") Link: https://lore.kernel.org/r/20241126075702.4099164-7-hongxing.zhu@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: ef61c7d8d032adb467f99d03ccfaa293b417ac75 commit ef61c7d8d032adb467f99d03ccfaa293b417ac75 Author: Richard Zhu <hongxing.zhu@nxp.com> Date: Tue Nov 26 15:56:57 2024 +0800 PCI: imx6: Deassert apps_reset in imx_pcie_deassert_core_reset() Since the apps_reset is asserted in imx_pcie_assert_core_reset(), it should be deasserted in imx_pcie_deassert_core_reset(). Fixes: 9b3fe679 ("PCI: imx6: Add code to support i.MX7D") Link: https://lore.kernel.org/r/20241126075702.4099164-6-hongxing.zhu@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: f068ffdd034c93f0c768acdc87d4d2d7023c1379 commit f068ffdd034c93f0c768acdc87d4d2d7023c1379 Author: Richard Zhu <hongxing.zhu@nxp.com> Date: Tue Nov 26 15:56:56 2024 +0800 PCI: imx6: Skip controller_id generation logic for i.MX7D The i.MX7D only has one PCIe controller, so controller_id should always be 0. The previous code is incorrect although yielding the correct result. Fix by removing "IMX7D" from the switch case branch. Fixes: 2d8ed461 ("PCI: imx6: Add support for i.MX8MQ") Link: https://lore.kernel.org/r/20241126075702.4099164-5-hongxing.zhu@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 7ab93e6a08d1c10bb2aad82dcb678a6c6ea65c20 commit 7ab93e6a08d1c10bb2aad82dcb678a6c6ea65c20 Author: Richard Zhu <hongxing.zhu@nxp.com> Date: Tue Nov 26 15:56:55 2024 +0800 PCI: imx6: Fetch dbi2 and iATU base addesses from DT Since dw_pcie_get_resources() gets the dbi2 and iATU base addresses from DT, remove the code from the imx6 driver that does the same. Upstream DTSes have not enabled Endpoint function. So nothing is broken for old upstream DTBs. Link: https://lore.kernel.org/r/20241126075702.4099164-4-hongxing.zhu@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: de22e20589b79f35f92543119c33051f8179dba0 commit de22e20589b79f35f92543119c33051f8179dba0 Author: Frank Li <Frank.Li@nxp.com> Date: Tue Nov 19 14:44:24 2024 -0500 PCI: imx6: Configure PHY based on Root Complex or Endpoint mode Pass PHY_MODE_PCIE_EP if the PCI controller operates in Endpoint (EP) mode, and fix the Root Complex (RC) mode being hardcoded using a drvdata mode check. Fixes: 8026f2d8 ("PCI: imx6: Call common PHY API to set mode, speed, and submode") Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-6-c4bfa5193288@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 137250911f4e58e3a5ba9caa91288e0d101f70c4 Conflict(s): Patching file drivers/pci/controller/dwc/pci-imx6.c: Hunk #5 FAILED at 1644. Same conflict as occured upstream and resolved in merge commit 5b9c74b635a6 "Merge branch 'pci/controller/imx6'". commit 137250911f4e58e3a5ba9caa91288e0d101f70c4 Author: Richard Zhu <hongxing.zhu@nxp.com> Date: Tue Nov 26 15:56:54 2024 +0800 PCI: imx6: Add Refclk for i.MX95 PCIe Add "ref" clock to enable Refclk. To avoid breaking DT backwards compatibility, the i.MX95 "ref" clock is optional. Use devm_clk_get_optional() to fetch i.MX95 PCIe optional clocks in driver. If using external clock, "ref" clock should point to external reference. If using internal clock, CREF_EN in LAST_TO_REG controls reference output, implemented in drivers/clk/imx/clk-imx95-blk-ctl.c. Link: https://lore.kernel.org/r/20241126075702.4099164-3-hongxing.zhu@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: d4627402bd04795b039cb652bf0c6792ad654a84 commit d4627402bd04795b039cb652bf0c6792ad654a84 Author: Richard Zhu <hongxing.zhu@nxp.com> Date: Tue Nov 26 15:56:53 2024 +0800 dt-bindings: PCI: fsl,imx6q-pcie: Add Refclk for i.MX95 RC Previous Refclk of i.MX95 PCIe RC is on when system boot to kernel. But boot firmware change the behavior, it is off when boot. So it must be turned on when it is used. Also it needs be turned off/on for suspend and resume. Add one Refclk for i.MX95 PCIe RC. Increase clocks' maxItems to 5 and keep the same restriction with other compatible string. Link: https://lore.kernel.org/r/20241126075702.4099164-2-hongxing.zhu@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 687aedb73a401addf151c5f60e481e574b4c9ad9 commit 687aedb73a401addf151c5f60e481e574b4c9ad9 Author: Frank Li <Frank.Li@nxp.com> Date: Tue Nov 19 14:44:25 2024 -0500 PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support Add support for the i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe Endpoint (EP). On the i.MX8Q platforms, the PCI bus addresses differ from the CPU addresses. However, the DesignWare (DWC) driver already handles this in the common code. Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-7-c4bfa5193288@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 3d2207256a373c510e4c29df0d4cfe9c1804b138 commit 3d2207256a373c510e4c29df0d4cfe9c1804b138 Author: Frank Li <Frank.Li@nxp.com> Date: Tue Nov 19 14:44:23 2024 -0500 dt-bindings: PCI: fsl,imx6q-pcie-ep: Add compatible string fsl,imx8q-pcie-ep Add new compatible string fsl,imx8q-pcie-ep for iMX8Q. The 'reg-names' property only needs 'dbi' and 'addr_space' because the others are located at a default offset. The new 'clock-names' property aligns with the Root Complex (RC) naming. Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-5-c4bfa5193288@nxp.com Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 1108d677dae296d2f05664bc71fd1d50bd61eb1f commit 1108d677dae296d2f05664bc71fd1d50bd61eb1f Author: Bjorn Helgaas <bhelgaas@google.com> Date: Fri Jan 17 17:51:19 2025 -0600 PCI: dwc: Simplify config resource lookup If platform_get_resource_byname("config") fails, return error immediately and unindent the normal path. No functional change intended. Link: https://lore.kernel.org/r/20250117235119.712043-1-helgaas@kernel.org Signed-off-by:
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Myron Stowe authored
JIRA: https://issues.redhat.com/browse/RHEL-83611 Upstream Status: 4dbf0155dfcfa65440b5f70d3e905261208b387e commit 4dbf0155dfcfa65440b5f70d3e905261208b387e Author: Frank Li <Frank.Li@nxp.com> Date: Tue Nov 19 14:44:19 2024 -0500 of: address: Add parent_bus_addr to struct of_pci_range Add a new field called 'parent_bus_addr' to struct of_pci_range to use when retrieving parent bus address information. Refer to the diagram below to better understand that the bus fabric in some systems (like i.MX8QXP) does not always use a 1:1 address map between input and output. Currently, many controller drivers use the cpu_addr_fixup() callback that would often hardcode address translation directly in the code, e.g., "cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR" or "cpu_addr + BUS_IATU_OFFSET", etc., even though those translations *should* be described via DT. However, the cpu_addr_fixup() can be eliminated if DT correctly reflects hardware behavior and drivers use 'parent_bus_addr' in struct of_pci_range. ┌─────────┐ ┌────────────┐ ┌─────┐ │ │ IA: 0x8ff8_0000 │ │ │ CPU ├───►│ ┌────►├─────────────────┐ │ PCI │ └─────┘ │ │ │ IA: 0x8ff0_0000 │ │ │ CPU Addr │ │ ┌─►├─────────────┐ │ │ Controller │ 0x7ff8_0000─┼───┘ │ │ │ │ │ │ │ │ │ │ │ │ │ PCI Addr 0x7ff0_0000─┼──────┘ │ │ └──► IOSpace ─┼────────────► │ │ │ │ │ 0 0x7000_0000─┼────────►├─────────┐ │ │ │ └─────────┘ │ └──────► CfgSpace ─┼────────────► BUS Fabric │ │ │ 0 │ │ │ └──────────► MemSpace ─┼────────────► IA: 0x8000_0000 │ │ 0x8000_0000 └────────────┘ bus@5f000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x80000000 0x0 0x70000000 0x10000000>; pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, <0x8ff00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; ... }; }; In the diagram above, the 'parent_bus_addr' field in struct of_pci_range can indicate internal address (IA) address information. Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-1-c4bfa5193288@nxp.com Signed-off-by:
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